1. Field of the Invention
The present invention relates to semiconductor wafer processing. More particularly, the present invention relates to vertical boats for holding semiconductor wafers during processing with minimum contact.
2. Description of the Related Art
Semiconductor wafers are conventionally processed by exposing surfaces of the wafers to gas in a high-temperature furnace. To maximize the amount of surface area exposed, wafers are carried in "boats". These boats may comprise parallel rods having slots evenly spaced along the length of the rods. Typically, the slots in one rod are aligned with the slots of the other rods so that a wafer can be jointly received by a corresponding slot from each rod. By placing wafers in the appropriate slots of the rods, the boat can carry a stack of wafers. The spacing between the slots along the rods separates the wafers from each other so that both sides of the wafers are exposed.
FIG. 1 illustrates a conventional boat 100, which comprises three rods 110 vertically extending from a base 120. As shown in FIG. 1, wafers 130 are held horizontally in the slots of rods 110. Rod 110 is shown in greater detail in FIG. 2, which illustrates rod 110 as having slots 112 evenly spaced along the length of rod 110. Slots 112 have top and bottom surfaces, designated by reference numerals 114 and 116, respectively. These surfaces are flat and substantially perpendicular to axis 118 of rod 100 (shown as a dotted line). Bottom surfaces 116 make planar surface contact with wafers placed in the respective slots.
These conventional slots, however, prevent portions of the wafer surfaces from being processed. For example, because the portions of the wafers contacting surfaces 116 remain covered, these portions are not exposed to the gas during processing and thus are not processed. Also, in some cases, top surfaces 114 may contact the wafer surfaces or otherwise prevent exposure to the gas, thereby preventing processing of those parts. This problem, known as "shadowing," results in valuable portions of the wafers not being processed, thereby reducing the amount of wafer surface area usable for semiconductor fabrication.